\section{Behavior}
\label{behavior}

For each output signal, the behavior should be the following:

\begin{itemize}
    \item \textbf{resp\_dcache\_cpu\_o:} this structure is used to send signals to the datapath and it has 8 signals:
    \begin{itemize}
        \item \textbf{lock}: the data cache is busy, and the datapath should be locked until the data cache finishes.
        \item \textbf{ready}: the data cache is ready to send the response.
        \item \textbf{data}: data to serve the load requests.
        \item \textbf{xcpt\_\{ma,pf\}\_\{st,ld\}}: 4 signals to indicate exceptions. \textit{ma} is misaligned, \textit{pf} is DTLB miss, \textit{st} is store, and \textit{ld} is load.
        \item \textbf{addr}: address of the exception.
    \end{itemize}
    \item \textbf{dmem\_req\_valid\_o:} sending a valid request to data cache.
    \item \textbf{dmem\_req\_cmd\_o:} type of the memory access: load, store, load-link, store-conditional, and atomic memory operations.
    \item \textbf{dmem\_req\_addr\_o:} address of the request.
    \item \textbf{dmem\_op\_type\_o:} granularity of the memory access: byte, halfword, and word.
    \item \textbf{dmem\_req\_data\_o:} data to store.
    \item \textbf{dmem\_req\_tag\_o:} tag of the memory access, only for multi-processor.
    \item \textbf{dmem\_req\_invalidate\_lr\_o:} reset load-link/store-conditional transaction.
    \item \textbf{dmem\_req\_kill\_o:} kill actual memory access.
\end{itemize}

The module has a state machine to manage the requests.
The state machine has 4 states:

\begin{itemize}
    \item \textbf{ResetState:} we reach this state when a reset signal arrives, i.e. when \textit{rstn\_i} becomes 0. It reset the state machine, going to \textit{Idle} state, and it cancels the requests to the Data Cache.
    \item \textbf{Idle:} we will stay in this state as long as there are no request from the datapath. If a request arrives from the datapath, we will move to \textit{MakeRequest}.
    \item \textbf{MakeRequest:} if a request arrives when we are in \textit{Idle}, we will move to this state. In this state, we make a request to the Data Cache, and we move immediately to \textit{WaitResponse}.
    \item \textbf{WaitResponse:} we will remain in this state until the Data Cache responds, and then, we will go to \textit{Idle} to wait a new request.
\end{itemize}

If during a request, a signal arrives killing the operation, the state machine will go to \textit{Idle}, and it will cancel the request in flight.

